Interposer structures and methods of manufacturing the same

ABSTRACT

Flexible and rigid interposers for use in the semiconductor industry and methods for manufacturing the same are described. Auto-catalytic processes are used to minimize the costs associated with the production of flexible interposers, while increasing the yield and lifetime. Electrical contact regions are easily isolated and the risk of corrosion is reduced because all portions of the interposer are plated at once. Leads projecting from the flexible portion of the interposers accommodate a greater variety of components to be tested. Rigid interposers include a pin projecting from a probe pad affixed to a substrate. The rigidity of the pin penetrates oxides on a contact pad to be tested. Readily available semiconductor materials and processes are used to manufacture the flexible and rigid interposers according to the invention. The flexible and rigid interposers can accommodate pitches down to 25 μm.

RELATED APPLICATIONS

This application is a continuation-in-part of, and claims priority to,U.S. patent application Ser. No. 10/909,111, filed on Jul. 30, 2004, nowabandoned.

FIELD OF THE INVENTION

This invention relates to interposer structures used in probingsemiconductor wafers and methods of fabricating the same.

BACKGROUND OF THE INVENTION

One of the final stages in the fabrication of integrated circuits onsemiconductor wafers is testing and sorting of the functionality of theindividual semiconductor chips, the dies. The purpose of testing thedies is to determine if the dies function as they were designed for;i.e., whether the dies produce intended outputs for given inputs. Oncefunctionality is established, the dies are sorted for operatingfrequency, i.e., the dies are ranked in terms of how fast each dieoperates. Due to the variations in processing steps, different diesfunction at different speeds.

There are a variety of techniques employed for testing the dies. One keyfactor in determining the method of testing the dies is the complexityof the device design. The number of input and output (I/O) pads presenton a die is often indicative of the complexity of the design, wherein ahigher number of I/O pads is attributed to higher design complexity.

A die with a low number of I/O pads arranged in a linear array can betested using probe stations where individual probe leads are broughtinto mechanical contact with each I/O pad. Typically, the number of padsin the linear array is less than, or on the order of, about 25. Theindividual probe leads provide power and input signals to the input padsand measures output signals from the output pads. For a die with amid-range number of I/O pads, customized probe cards with many probeleads can be generated wherein the probe leads are arranged tocorrespond to each I/O pad on the mid-range die. The customized probecards may also be wired and connected to a tester to provide power andinput signals and analyze output signals from the die. For a die with ahigh number of I/O pads, i.e., those having hundreds to thousands of I/Opads typically in an aerial array, customized probe cards connecting thedie to a tester is impractical and expensive, and in some instancesimpossible. An economical alternative is needed.

Where testing or measuring of the die with customized probe cards isimpractical for a die with a high number of I/O pads, it is oftenadvantageous to use packaging mounts, e.g., ceramic or organic modulesin which the die to be tested may be mounted, in order to facilitatetesting of the die. In this way, wiring from the I/O pads of the dieunder test to tester compatible pin of the packaging mount is readilyavailable. The temporary wiring, or electrical connections of the I/Opads of the die to the packaging mounts is preferred over permanentpackaging of the die since the costly process of forming the permanentpackaging may be avoided should the die under test be found defective.

Interposers are devices commonly used in manufacturing for formingtemporary electronic connections for the purpose of probing of asemiconductor die with a high number of I/O pads. FIG. 1 is a schematicview of a system in which an interposer 100 provides an electricalconnection between a tester 110 and a semiconductor wafer 120. Suchinterposers offer a convenient way of testing electronic components,such as semiconductor wafers, without requiring a permanent electricalconnection, such as solder bonds, between the electronic components anda tester. A permanent electrical connection, such as a die packaging,would have to be dismantled or discarded were the tested componentdeemed defective. Thus, such interposers often provide a method ofeconomically determining the functionality of semiconductor wafers orsemiconductor dies in the semiconductor industry.

Interposers currently in use for testing of semiconductor wafers may beelectrolytic plated interposers designed to probe rigid, non-evensurfaces such as those commonly associated with ceramic packagingmodules. Flexible interposers, which may probe non-rigid surfaces, thatare currently available are difficult and cost-prohibitive to fabricate,and requires unusual processing techniques that are not readilypracticed. Currently available interposers tend to target rigidsubstrates, such as silicon dies or silicon substrates.

Thus, current interposers also fail to facilitate probing of flexiblesubstrates that are becoming more common with the use of organicsemiconductor materials and flexible substrate materials.

Therefore, there exists a need for a flexible interposer structure forprobing flexible, non-rigid semiconductor dies and methods offabricating the same.

There also exists a need for a more economical interposer structure forprobing rigid surfaces and methods of fabricating the same.

SUMMARY OF THE INVENTION

The present invention provides structures for interposers for use withrigid or flexible substrates and methods for fabricating the same in acost-effective and convenient manner.

Some embodiments of the present invention comprise structures forflexible interposers and methods of fabricating the same while reducingexternal power supply needs. Methods are provided for fabricating theflexible interposers while reducing precious metals waste. Methods arealso provided for fabricating the flexible interposers with minimalnodule formations. These embodiments of the present invention furtherprovide methods for fabricating electroless plated flexible interposersusing commercially available electroless metal plating baths.

Other embodiments of the present invention provide methods forfabricating flexible interposers using standard semiconductor processesto improve yield and reduce processing costs. These embodiments of theinvention provide for tighter pitches in the interposers than do currenttechnologies, and better facilitate the probing of non-uniform substratesurfaces.

Still other embodiments of the present invention provide methods offabricating a rigid interposer. The rigid interposer better facilitatesprobing and testing of flexible substrates.

According to an aspect of the present invention, methods for fabricatinginterposers are provided. A first method for fabricating a flexibleinterposer comprises:

providing a flexible interposer panel containing:

-   -   a flexible insulator sheet;    -   pre-plating bumps on one side of the flexible insulator sheet;    -   a metal sheet located on another side of the flexible insulator        sheet, wherein the pre-plating bumps are connected to the metal        sheet through conductive vias;

applying a grayscale photoresist layer for grayscale lithography on themetal sheet;

etching the metal sheet to form pins under the pre-plated bumps;

dicing a plurality of flexible interposer templates out of the flexibleinsulator panel;

seeding one of the flexible interposer templates with a first metal;

depositing an electroless layer comprised of a second metal on theflexible interposer template by immersion-seeding in a bath providedwith a second metal, wherein the second metal is more noble than thefirst metal; and

depositing a third metal onto the electroless layer, wherein the thirdmetal is more noble than the second metal.

The cleaning of the surface may further comprise:

stripping the surface of organics and the photoresist;

oxygen-ashing the surface;

soaking the surface in ethyl alcohol;

rinsing the surface with de-ionized water; and

rendering the surface catalytic.

The method may further comprise holding the flexible interposer in aflexible interposer holder during fabrication of the flexibleinterposer, wherein the flexible interposer holder is comprised of apolymer. The surface of the flexible interposer panel may be Cu, thefirst metal may be Pd, the second metal may be Ni, and the third metalmay be Au.

The depositing of the third metal may comprise:

depositing a first immersion layer of the third metal onto the flexibleinterposer; and

depositing a second electroless plating layer of the third metaldirectly onto the first immersion layer.

The bath may be constantly agitated and filtered to accommodate moreuniform and smooth deposits. The electroless plated layer may be locatedon both sides of the flexible insulator template. The method may furthercomprise cleaning, etching and re-plating the flexible interposer asneeded to increase the lifetime of the flexible interposer. Theelectroless layer may be deposited on all sides of the flexibleinterposer at once.

A second method of fabricating a flexible interposer comprises:

forming a bonded wafer by bonding a thinned wafer to a handle wafer withan adhesion layer therebetween, wherein the handle wafer is selectedfrom the group consisting of a quartz wafer and a silicon wafer;

etching cavities in the shape of inverted pyramids into an exposedsurface of the thinned wafer within the bonded wafer using ananisotropic etching process;

forming flexible leads by depositing a seed layer atop the exposedsurface of the thin wafer and patterning the seed layer;

forming and patterning an insulating layer over the flexible leads toform joining studs the protrude above the insulating layer;

providing a substrate having a top surface and a bottom surface whereinfirst via holes extends through the substrate between the top surfaceand the bottom surfaces thereof, and second via holes that areanisotropically etched on the bottom surface of the substrate;

filling the first via holes with a conductive material to form firstvias;

forming a substrate insulating layer on the bottom surface of thesubstrate, the substrate insulating layer having third via holes thatalign with the first vias for receiving of the joining studs;

joining the substrate with the bonded wafer, whereby the joining studsare received in the third via holes of the substrate insulating layerand contacts the first vias;

adding metal contacts to the top surface of the substrate; and

removing the thinned wafer, the handle wafer, and at least a portion ofthe insulating layer.

The method may further comprise fabricating wiring structures on themetal contacts. The wiring structures may be contacted using wirebondingtechniques. Each of the thinned wafer and the handle wafer may be asilicon substrate. Alternatively, each of the thinned wafer and thehandle wafer is a quartz wafer.

The flexible leads may comprise an elastic metal coated with aconductive metal, the combination thereof having a high tensile strengthin the range of 450-620 Mpa. The flexible leads may comprise one of BeCuand W. The flexible leads may comprise an elastic polymer having a metalor metallic coating. The flexible leads comprise a rigid material, whichmay comprise one of silicon or Si3N4 having a conductive or metalliccoating. The flexible leads may have a pitch from about 25 μm to about400 μm.

Multiple cavities may be etched in a cluster during the etching of thecavities for each of the flexible leads. The multiple cavities maycomprise an array of cavities. The insulating layer may be an elasticpolymer.

The method may further comprise providing a mechanical structure on thesubstrate for facilitating mechanical alignment of the flexibleinterposer with a component to be tested. The cavities may beanisotropically etched to form molds. The method may further comprisefilling the molds with a conductive material by a technique selectedfrom at least one of electroplating, electroless plating, and screening.The molds may be filled with a hard material selected from the groupconsisting of PdNi and PdCo.

A method for fabricating a rigid interposer comprises:

etching via holes in a wafer;

filling the via holes with a conductive material to form conductivevias;

depositing a metal layer directly on the conductive vias and the waferthereby forming a wafer/metal layer combination;

thinning the wafer/metal layer combination to expose bottom surfaces ofthe conductive vias;

providing metal contacts on the exposed bottom surfaces of theconductive vias; and

patterning and etching probes having projecting pins out of the metallayer.

The method may further comprise fabricating wiring structures on one ormore surfaces of the metal contacts. The wiring structures may becontacted using wirebonding techniques. The wafer may comprise silicon.The probes may have a pitch from about 25 μm to about 400 μm, and theprobes have a sharp point that may penetrate oxides on contact pads of acomponent to be tested. The pins may comprise a hard material selectedfrom the group consisting of PdNi and PdCo.

According to another aspect of the present invention, flexibleinterposers and a rigid interposer are provided. A first flexibleinterposer comprises:

a flexible interposer panel comprising an insulator;

at least one probe located on the flexible interposer panel and seededwith a first metal;

a first electroless plated layer comprising a second metal that overliesthe first metal; and

a second electroless plated layer comprising a third metal that overliesthe second metal.

The at least one probe comprises copper, the third metal iselectrochemically more noble than the second metal, and the second metalis electrochemically more noble than the first metal. The first metalmay be Cu seeded with Pd the second metal may be Ni, and the third metalmay be Au.

The first electroless plated layer and the second electroless platedlayer may be located on both sides of the flexible interposer panel. Thefirst flexible interposer may further comprise electrically isolatedregions located between the at least one probe, wherein the at least oneprobe is a plurality of probes.

A second flexible interposer comprises:

a substrate having a top surface and a bottom surface wherein first viascomprising a conductive material extend through the substrate betweenthe top surface and the bottom surfaces thereof, and a second set of viaholes that are anisotropically etched along the bottom surface of thesubstrate;

a substrate insulating layer located on the bottom surface of thesubstrate, the substrate insulating layer having third via holesunderneath a portion of the first vias;

at least one flexible lead having a tip in the shape of an invertedpyramid and a joining stud abutting one of the first vias through one ofthe third via holes; and

contacts to the top surface of the substrate.

The at least one flexible lead may be cantilevered from the substrate.The second flexible interposer may further comprise wiring structureslocated on the metal contacts.

Each of the at least one flexible lead may comprise an elastic metalcoated with a conductive metal, wherein the combination of the elasticmetal and the conductive metal has high tensile properties. Each of theat least one flexible lead may comprise an elastic polymer having ametal or metallic coating. Each of the at least one flexible lead maycomprise one of BeCu, W, Si and Si3N4. Each of the at least one flexiblelead may comprise a rigid material. The at least one flexible lead maybe a plurality of flexible leads having a pitch from about 25 μm toabout 400 μm. Each of the at least one flexible lead may have multipletips in the shape of inverted pyramids. The multiple tips may comprisean array for contacting a bump to be probed.

A rigid interposer comprises:

a wafer having a top surface and a bottom surface;

conductive vias comprising a conductive material, located within thewafer, and extending from the top surface to the bottom surface;

metal contacts abutting the conductive vias and the bottom surface; and

probes having projecting pins and abutting the conductive vias and thetop surface.

The rigid interposer may further comprise wiring structures located onthe metal contacts. The wiring structures may be contacted usingwirebonding techniques. The probes may have a pitch from about 25 μm toabout 400 μm. The wafer may comprise Si. Each of the probes may comprisea metal pad having the projecting pins, wherein the projecting pins maypenetrate oxides on contact pads of a component to be tested. Theprojecting pins may comprise a hard material selected from the groupconsisting of PdNi and PdCo.

One of ordinary skill in the art should appreciate that interposers canbe designed to reduce oxidation of tester components, to increaseflexibility of tester components, and to overcome mismatch betweenconnected tester components. Accordingly, the interposers and methods ofmanufacturing the same, as described herein, are understood toaccommodate these aspects as well.

The above and other features of the present invention, including variousnovel details of construction and combination of parts, will be moreparticularly described with reference to the accompanying drawings andclaims. It will be understood that the various embodiments of thepresent invention described herein are shown by way of illustration onlyand not as a limitation thereof. The principles and features of theinvention may be employed in various alternative embodiments withoutdeparting from the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects and advantages of the systems andmethods of the invention will become better understood with regard tothe following description, drawings, and appended claims, wherein:

FIG. 1 shows a conventional flexible interposer connecting an electroniccomponent to a wafer.

FIGS. 2A-2I show a first flexible interposer at various stages ofmanufacturing process according to an embodiment of the presentinvention. FIG. 2A is a top-down at the step corresponding to FIG. 2B.FIG. 2C is a bottom view at the step corresponding to FIG. 2D. FIGS. 2B,2D-2I are sequential cross-sectional views along the plane correspondingto B-B′ in FIG. 2A or FIG. 2C. FIG. 2B is a cross-section of FIG. 2A andFIG. 2D is a cross-section of FIG. 2C.

FIG. 3 shows a scanning electron micrograph (SEM) micrograph of a crosssection of a surface of an electroless plated probe according to thepresent invention.

FIGS. 4A-4I show a second flexible interposer at various stages ofmanufacturing process according to another embodiment of the presentinvention.

FIGS. 5A-5F show a rigid interposer at various stages of manufacturingprocess according to a further embodiment of the present invention.

FIG. 6 illustrates an embodiment of a probe for use with a rigidinterposer according to the invention.

FIG. 7 illustrates a scanning electron micrograph (SEM) of anelectroless plated probe.

DETAILED DESCRIPTION OF THE INVENTION

Electroless plating refers to the autocatalytic reduction of a metal ionat a cathodic surface. The metal ion in solution reduces at the surfaceof the work piece through a parallel oxidation reaction. For example, ahypophosphite anion can be oxidized according to the following reaction:

$\begin{matrix}\begin{matrix}{{{Ni}^{2 +} + {2\; e^{-}}}->{Ni}^{0}} \\{{{H_{2}{PO}_{2}^{-}} + {H_{2}O}}->{{H_{2}{PO}_{3}^{-}} + {2\; H^{+}} + {2\; e^{-}}}} \\{{{Ni}^{2 +} + {H_{2}{PO}_{2}^{-}} + {H_{2}O}}->{{Ni}_{({metal})} + {2\; H^{+}} + {H_{2}{PO}_{3}^{-}}}}\end{matrix} & \left( {{Equation}\mspace{14mu} 1} \right)\end{matrix}$

Equation 1 renders hydrogen evolution as a result of the platingprocess. Excess hydrogen production can interfere with the quality ofthe plated film, however, and should be avoided by proper bath agitationand/or additions of surface dewetting agents. Commercially availableelectroless solutions contain stabilizers to control the reaction ratesof Equation 1. Electroless plating baths also contain various metalsalts, reducing agents and organics to buffer and maintain the solutionas well as to adjust properties such as hardness and the appearance ofdeposits in the plating film. The advantage of the reaction of Equation1 is that it does not rely on an external supply of electrons to reducethe metal ions. As a result, conformal depositions may occur on anyactive surface.

Some embodiments of the present invention comprise an electrolessplating process for fabricating flexible interposer probes. According tothese embodiments, the electroless plating process uses conformal metalcoatings without external power supplies or complicated commoningmethods. Because no external power source is used, nodule formations areminimized. Such nodule formations tend to occur at points of highcurrent densities, e.g., at sharp edges, when forming flexibleinterposer probes using standard electrolytic plating techniques.Further, because electroless plating solutions of the invention contactall parts of the interposer, electrically isolated regions need not beelectrically connected to one another by a commoning layer, such as adeposited thin film of Cu, for example. Further still, the electrolessplating techniques described herein improve the manufacturability andreduce the cost of interposers as compared to known interposerfabricating technologies.

Electroless plating, according to the present invention, begins byforming a surface that is clean and catalytic. The artisan willappreciate that numerous techniques exist for creating an autocatalyticsurface with a variety of chemicals, though for brevity the discussionherein focuses on those chemicals most suited for electroless depositionon copper as most probe panels use copper as its plating surface. Thestandard method of creating a catalytic surface is by utilizing animmersion, or displacement, deposit of a more noble and catalytic metalsuch as zinc (Zn), palladium (Pd), or tin (Sn).

The galvanic series, or electropotential series, known in chemistrydetermines the nobility of metals and semi-metals. When two metals aresubmerged in an electrolyte, while electrically connected, the lessnoble metal will experience galvanic corrosion. The rate of corrosion isdetermined by the electrolyte and the difference in nobility. Thedifference can be measured as a difference in voltage potential.Galvanic reaction is the principle on which batteries are based.

The following is a galvanic series for stagnant seawater, that is, waterhaving low oxygen content, for a selection of elemental metal and metalcompounds. The elements are listed in the order of decreasing nobleness,i.e., from the most noble element in the beginning to the least nobleelement at the end. Graphite, Palladium, Platinum, Gold, Silver,Titanium, Stainless steel (316 passive), Stainless Steel (304 passive),Silicon bronze, Stainless Steel (316 active), Monel 400, Phosphorbronze, Admiralty brass, Cupronickel, Molybdenum, Red brass, Brassplating, Yellow brass, Naval brass 464, Uranium with 8% Mo, Niobium with1% Zr, Tungsten, Stainless Steel (304 active), Tantalum, Chromium,Nickel (passive), Copper, Nickel (active), Cast iron, Steel, Lead, Tin,Indium, Aluminum, Uranium (pure), Cadmium, Beryllium, Zinc, andMagnesium.

For description of the present invention, the order of decreasingnobleness in stagnant sea water as listed above is employed. It isnoted, however, that the order may change in different environments andthat the present invention may be practiced when relativeelectrochemical nobleness of elements are altered in a differentenvironment, i.e., in a solution with a different composition.

Displacement deposits occur when a metal surface with a lower freeenergy, i.e., electrochemically less noble, is placed into a solutioncontaining metal ions that are at a higher free energy, i.e., morenoble. The difference in the thermodynamic free energies drives thereaction that replaces the metal atom on the surface with the metalatoms from the solution. The kinetics of the reaction are governed bythe fractional surface coverage of the replacement atom on the surface.As the fractional coverage of the surface increases, the reaction slowsdown. A typical example of this reaction is that of a Cu metal surfacebeing displaced by Pd atoms from an acidic solution. The reaction isdescribed by Equation 2 below:

$\begin{matrix}{{Cu} + {Pd}^{2 +} + {{SO}_{4}^{2 -}\overset{{pH} < 7}{\longrightarrow}{Pd}} + {Cu}^{2 +} + {SO}_{4}^{2 -}} & \left( {{Equation}\mspace{14mu} 2} \right)\end{matrix}$

In the above reaction described by Equation 2, the Cu atoms on theplating surface are displaced by the Pd atom because of a reactionpotential of −1.293 V driving the Pd atom to cover the surface. The pHof the solution is adjusted to be acidic by the addition of sulfuricacid, for example. The acid helps to prevent oxidation at the Cu surfaceand favors the removal of Cu metal as copper sulfate. The reaction ofEquation 2 will cease once the surface has been fully covered with Pdatoms. Immersion deposits can range from a few hundreds of angstroms toa few microns in thickness depending on the metal systems used.

Table 1 below illustrates chemistries and processes used in theproduction of electroless plated probes according to some embodiments ofthe invention.

TABLE 1 Electroless plating chemistries used in the production ofprobes. (Cu Preclean Procedure: Strip all resist coatings, Soak in EthylAlcohol with ultrasonic agitation for 5 minutes, DI Water Rinse, OxygenAsh at 100 W for 5 min in 650 mTorr of O²) ENPLATE NI426 Oromerse MNGobright TMX-21 Operating Operating Operating temperature: 83° C.Temperature: 70° C. Temperature: 55° C. Operating pH = 6.2 Operating pH= 5.5 Operating pH = 7.4 Optimal plating Optimal plating Optimal Platingrate = 15-18 μm/hr rate = 5-7 nm/min Rate = 1.5 μm/hour @85° C. MaximumAu Thickness = Minimal part agitation 0.3 μm

According to an aspect of the present invention, there are five primarysteps to the electroless plating process according to the invention. Thesteps generally are:

-   -   1. pre-cleaning an interposer template    -   2. seeding the interposer template    -   3. depositing a first electroless layer on the interposer        template    -   4. immersion seeding the interposer template    -   5. depositing a second electroless layer on the interposer        template.        For example, the initial seeding is Pd seeding, the initial        electroless layer Ni, the immersion seeding is Au, and last        electroless layer is Au.

Referring to FIGS. 2A-2B, a flexible interposer panel is provided whichcontains a flexible insulator sheet 201 with pre-plating bumps 202 onone side and a metal sheet 203 on the other side. FIG. 2A is a top-downview of the flexible interposer panel. FIG. 2B is a verticalcross-sectional view of the flexible interposer panel along the planeB-B′ in FIG. 2A. The pre-plating bumps 202 are connected to the metalsheet 203 through conductive vias 204. The pre-plating bumps 202 may beformed by depositing a layer of metal followed by a lithographicpatterning and etching. Preferably, each of the pre-plating bumps 202 isconnected to the metal sheet 203 by one of the conductive vias 204. Thepre-plating bumps 202 may comprise copper.

Referring to FIGS. 2C-2D, a spin-on photoresist 205 or a dry filmlaminate is applied to protect the pre-plating bumps 202 from agrayscale etching solution, while a grayscale photoresist 206 is appliedonto the metal sheet 203 and is patterned. FIG. 2C is a verticalcross-sectional view of the flexible interposer panel along the planeB-B′ in FIG. 2D. FIG. 2D is a bottom view of the flexible interposerpanel. A plurality of flexible interposer sheets may be cut, forexample, from the flexible interposer panel, which may have, forexample, a four-up configuration.

Referring to FIG. 2E, a vertical cross-sectional view of one of theflexible interposer sheet is shown after the grayscale lithography,etching, and the cut-up. Pins 207 are formed out of the metal sheet 203after the etching.

The flexible interposer sheet is at this point loaded onto a flexibleinterposer holder (not shown), which may be a custom designed, Delrin®probe holder. Preferably, the flexible interposer holder is madecompletely of at least one polymer material to avoid plating onto anymetal parts. The flexible interposer sheet may be fixed by dowel pinholes and held in a semi-rigid manner. Holding the flexible interposersheet in this manner helps keep the flexible interposer sheet in asteady position in the baths.

Experimentation of the processes according to the present invention hasdetermined that a clean Cu surface is required for proper Pd seeding andelectroless Ni deposition. It is also preferable to strip any organicsfrom the Cu surfaces because the flexible interposer sheet is treatedwith a benzotriazole solution and other organic chemicals during theirproduction. The flexible interposer sheet is soaked in ethyl alcohol andrinsed in de-ionized (DI) water. The parts are then be oxygen ashedprior to plating to remove any residual organic compounds.

Referring to FIG. 2F, the spin-on photoresist 205 is removed from theflexible interposer sheet. For example, a Branson® barrel asheroperating at a frequency of 13.56 MHz and 100 W of power for 10 minutesin a flowing oxygen atmosphere at a pressure of 650 mTorr may beemployed. The ashed flexible interposer sheet is then dipped into a 25%sulfuric acid solution for 2 minutes to remove any oxidized copper.

Referring to FIG. 2G, the flexible interposer sheet may then be rinsedin flowing DI water for 30 seconds and dipped into a seeding bath (notshown) for seeding a first metal to form a seeding layer 211. The firstmetal may be Pd and the seeding bath may be, for example, an acidicpalladium sulfate seeding bath (0.1 g/L PdSO₄ in 20 mL/L H2SO₄ aqueoussolution) and the duration of seeding may last for 5 minutes. This tendsto produce a dark tarnish of Pd atoms on the Cu surfaces. Finally, theflexible interposer sheet is rinsed in DI water for 30 seconds to removeany excess Pd seed or acid.

Referring to FIG. 2H, the seeding layer 211, located on the pre-platingbumps 202 and the pins 207 and now having active metallic surfaces, isimmersed into an electroless metal bath (not shown) to deposit anelectroless layer 212 of a second metal. The electroless metal bath maybe an electroless nickel (EN) bath and the second metal may be Ni. TheEN bath used in the experimentation of the invention was ENPLATE NI426,which is a low phosphorous plating bath produced by Enthone Corporation.Operating conditions of the EN bath are given in Table 1. According tothese conditions, a Ni—P phase diagram should indicate that no solidsolubility of phosphorous in Ni at the plating temperature exists andthat only a mixture of pure Ni and the intermetallic Ni₃P exists.However, because of the plating rate, it is kinetically impossible forthe intermetallic phase to form. Therefore the electroless layer 212 maybe a supersaturated alloy of Ni and P. This results in a very hard(650HK100) deposit with a microcrystalline grain structure (grain sizes2 to 6 μm).

The electroless plating bath is operated under constant agitation andfiltration to ensure uniform and smooth deposits. Custom plating tanksand bath heaters are used to accommodate the panels. At a pH of 6.2 anda bath temperature of 83 degrees C., the plating rate is between 15 and18 μm/hr. Parts are left in the bath for 10 minutes to achieve a 2.5 μmfilm. The film thicknesses can be confirmed using optical microscopy andSEM imaging. Conformal coverage of the underlying Cu produces a coherentand smooth Ni:P film.

Referring to FIG. 2I, a similar thickness of a third metal iselectroplated to ensure good electrical contact for testing. The thirdmetal forms a third metal layer 213 and may be gold (Au). The thirdmetal layer 213 may be formed by a two-step process where a first layerof immersion gold is deposited to a thickness of 0.3 μm, followed by anelectroless gold deposition of 2.2 μm to form a second layer ofimmersion gold. The immersion Au chemistry used may be Oromerse MN® fromTechinc Incorporated, and the electroless Au bath may be the GoBrightTMS-21 ® bath from Uyemura International Corporation. Both baths comepremixed and ready to use. The operating details are given in Table 1above. The finished flexible interposer sheet becomes a flexibleinterposer.

In a simple modification of the standard flexible interposer fabricationprocess that is described above, the two-step bump/grayscale plating isreplaced with a single electroless plating process. The new process canbe broken down into three components:

-   -   1. pre-plating bump and pin formation;    -   2. flexible interposer sheet removal and cleaning; and    -   3. electroless deposition of Ni/Au layers on the flexible        interposer sheet.

The first stage of the flexible interposer fabrication process is theformation of the pre-plating bumps 202 and the pins 207. These should beformed using the standard process as a template with the followingmodifications. First, pre-plating bumps 202 are formed on a flexibleinterposer panel. The pre-plating bumps are formed with a standardheight and width, as dictated by the original process. The pre-platingbumps 202 may comprise Cu. The pre-plating bumps 202 are protected witha thick resist coat applied by a brush and air dried. The metal sheet203 are cleaned and coated with a grayscale resist, as required forgrayscale lithography and etching. The standard etch procedure is usedto form pins 207. The final product is a flexible interposer panel withpre-plating humps 202 on one side and pins 207 on the opposite side. Theflexible interposer panel may contain a plurality of flexible interposersheets. For example, the flexible interposer panel may be a four-upsheet having four flexible interposer sheets.

At this point, the individual flexible interposer sheets are cut out ofthe flexible interposer panel to reduce Ni and Au plating waste. Eachflexible interposer sheet is then cut from the flexible interposer paneland cleaned to ensure that all organics are removed before electrolessplating begins. The electroless deposition of Ni and Au is thenperformed.

The following process and solutions, for example, may be used to produceflexible interposers according to the invention:

-   -   1. Dip a flexible interposer sheet into 25% H₂SO₄ for 2 minutes        and rinse with DI water for 30 seconds.    -   2. Dip the flexible interposer sheet into Pd seed solution for 4        minutes and rinse for 30 seconds.    -   3. Dip the flexible interposer sheet into ENPLATE Ni426® plating        solution for 12 minutes and rinse for 1 minute (the metal probes        should be shiny and silver colored now).    -   4. Dip the flexible interposer sheet into Oromerse MN® solution        for 30 minutes and rinse for 30 seconds (0.2˜0.3 μm Au film        achieved).    -   5. Dip the flexible interposer sheet into Gobright® solution for        90 minutes (2.2˜2.3 μm film achieved).

FIG. 3 shows an SEM micrograph of the cross section of a surface of theflexible interposer sheet. The top two layers in the image are theelectroless Au layer 233 and the electroless Ni layer 232. Note theuniformity of the coverage. The electroless Ni layer 232 measuresapproximately 3.0 μm and the electroless Au layer 233 measuresapproximately 2.5 μm. Although not shown, the electroless Ni layer 232is seen to penetrate into the micro-roughened Cu surface at highermagnifications. This penetration forms a strong interface between the Niand Cu surfaces.

The above described processes offer several advantages over otherfabrication methods. For example, the underside of the flexibleinterposer panel that contacts the grayscale photoresist 206 is platedwith a stack of protective layers, i.e., a stack of the electroless Nilayer 212 and the electroless Au layer 213. In standard electrolyticplating, this part of an interposer would not be coated, and wouldtherefore be subject to corrosion and other degradation. Acidic agentsare typically used to clean currently available interposers according tostrict cleaning schedules in order to remove lead and tin deposits, forexample. Such acidic agents are often a primary cause of corrosion on anunderside of the probes. Eliminating the need for these acidic agentsrenders the probes fabricated by the processes described herein morereliable and more convenient as well.

The flexible interposers fabricated by the electroless plating processesdescribed herein are more easily repaired than currently availableinterposers as well, particularly where the interposers have alreadybeen used and/or have suffered damage to the stack of protective layers.Once a damaged probe is identified, it can be cleaned and replated withanother stack of an electroless Ni layer and an electroless Au layer asthe original stack of protective layer (212, 213) wears thin or wearsout. This process of repair can significantly increase the lifetime ofthe flexible interposer, and can lower the cost of use as well.

Further, the flexible interposers fabricated by the electroless platingprocesses described herein may be produced in less steps than currentlyavailable interposers. For example, where standard electrolytic platingmethods are used, the front side of the interposer and the back side ofthe interposer are each separately plated. Thus, the electrolyticplating process requires two separate plating procedures for the priorart interposers. On the other hand, the electroless plating processesdescribed herein coats both sides of the flexible interposer at once,thereby saving a significant amount of processing steps.

FIGS. 4A-4H, as will be described in more detail below, illustrateanother embodiment of fabricating a flexible interposer according to theinvention. In general, the flexible interposer fabricating processillustrated in FIGS. 4A-4H use standard semiconductor processes andmaterials, as opposed to the more complex procedures and uncommonmaterials often used to produce currently available flexibleinterposers.

Referring to FIG. 4A, a thinned wafer 300 is bonded to a handle wafer310 with an adhesion layer 305 therebetween. The thinned silicon wafer300 may be obtained by thinning a silicon wafer with a normal thickness,e.g., about 800 microns. The handle wafer 310 may be a quartz wafer or aSi wafer. Likewise, the tinned wafer 300 may be a quartz wafer or a Siwafer. The adhesion layer 305 may be an oxide layer or an organicadhesion layer comprising an organic material such as Dupont KJ.

Referring to FIG. 4B, cavities 315 in the shape of inverted pyramids areformed on the exposed top surface of the thinned wafer 300. The cavities315 may be formed using an anisotropic etch process, for example. Thecavities 315 form molds for pins of flexible leads. One of ordinaryskill in the art will appreciate that additional multiple cavities, orother shapes, may be formed in a cluster during the etching of thecavities 315. The additional multiple cavities may comprise an array ofcavities.

Referring to FIG. 4C, a seed layer 321 is deposited atop the exposedsurface of the thinned wafer 300 and fills the cavities 315 in the shapeof the inverted pyramids. The molds, which are cavities 315, are filledwith a conductive material by a technique selected from at least one ofelectroplating, electroless plating, and screening. The molds may befilled with a hard material selected from the group consisting of PdNiand PdCo.

The molds are filled with a material, such as a metal, up to aprescribed thickness to create sharp pins. This molding techniqueprovides advantages such as:

producing atomically sharp features using silicon or other singlecrystalline materials (GaAs, Ge, SiGe, and others);

permitting easier image replication using materials that are easilypeeled away, such as Cu, that does not bond well with a Si mold;

providing cleaning of the mold using standard semi-conductor techniques;and

providing economical production methods.

Referring to FIG. 4D, the seed layer 321 is lithographically patternedand etched to form flexible leads 320 and joining studs 335. Preferably,each of the flexible leads 320 has a pin which is formed out of one ofthe molds. The joining studs 335 protrude out of the flexible leads 320.Preferable, each of the flexible leads 320 also has a cantilever portionto which the pin is attached.

An insulating layer 330 is deposited and patterned over the flexibleleads 320 such that joining studs 335 protrude above and surrounded bythe insulating layer 330. The insulating layer 330 may be an elasticpolymer.

The flexible leads 320 are preferably created using either a flexibleorganic material coated with a conductive metal, or a metal with goodelectrical properties while possessing high tensile strength such as,for example, 450-620 MPa and most preferably about 550 MPa. For example,copper beryllium (CuBe) could be used as the material for the flexibleleads 320, or an elastic polymer having a metal or metallic coatingcould be used, although other flexible organic materials known in theart could as well be used as will be appreciated by the skilled artisan.One of ordinary skill in the art will also readily appreciate that theflexible leads 320 could as well be comprised of a more rigid materialsuch as, Si or Si₃N₄, for example.

The flexible leads 320 may be employed, for example, to contact solderpads be formed on one side of the interposer to connect to the firstvias. The flexible leads 320 are rigid enough to puncture through oxideson the surface of the solder ball to accommodate any non-uniformity inheights.

Referring to FIG. 4E, a substrate 340, which may be a silicon wafer,having a top surface and a bottom surface is provided. First via holesare formed through a semiconductor wafer 340. The first via holes arefilled with a conductive material, for example, to form first vias 345.The first vias permit a front-to-back connection through thesemiconductor substrate 340. The first vias 345 thus connect twostructures above and below the semiconductor substrate 340. Depending onthe application, the first vias 345 can be built on both sides of thewafer in order to better facilitate probing. Second via holes 346 areanisotropically etched on a bottom surface of the substrate 340.

Referring to FIG. 4F, a substrate insulating layer 360 is formed on thebottom surface of the substrate 340. The substrate insulating layer 360is patterned and etched to form extension via holes such that extensionvias 365 are formed on the first vias 345 by deposition of a conductormaterial. Alternatively, the bottom surface of the substrate 340 may berecessed prior to deposition of the substrate insulating layer 360 andplanarized after the deposition of the substrate insulating layer 360 toexpose the first vias 340. In this case, the extension vias 365 areportions of the first vias 345.

The substrate insulating layer 360 and the extension vias 365 have thirdvia holes that align with the joining studs 335 on the bonded wafer forreceiving the joining studs 335.

Referring to FIG. 4G, the substrate 340 joined to the bonded wafercomprising the handle wafer 310, the adhesion layer 305, the thinnedwafer 300, the flexible leads 320, the insulating layer 330, and thejoining studs 335, whereby joining studs 335 are received in theextension vias 365 within the insulating layer 360 that are aligned withthe first vias 345 of the substrate 340. Metal contacts 347 are added tothe top surface of the substrate 340.

Referring to FIG. 4H, the handle wafer 310, the adhesion layer 305, thethinned wafer 300, and at least a portion of the insulating layer 330are etched. All of the insulating layer 330 may be etched to leave aflexible interposer according to the present invention.

Referring to FIG. 4I, a variation of the flexible interposer structurecomprises flexible leads 320 with multiple pins 316. The multiple pins316 may be formed by etching multiple cavities in a cluster during theformation of the cavities 315. The multiple pins 316 may comprise anarray of pins.

The flexible interposer formed by the processes described above withrespect to FIGS. 4A-4I use standard semiconductor processes andmaterials and employs micro-molds. These flexible interposers are thuscheaper and easier to manufacture than existing interposers which areeither hand-assembled or require non-standard processing of organicsubstrates. The flexible interposers formed according to the processesset forth in FIGS. 4A-4I, for example, may also demonstrate improvedpitch including smaller pitches than prior art interposers exhibit. Theinterposer according to the invention may accommodate probing fine pitchpads having pitches of as little as 25 μm, for example. The range ofpitches that the flexible interposer may accommodate may be from about25 μm to about 400 μm. Further still, the processes set forth in FIGS.4A-4I could also be used to serve as arrays of metallic atomic forcemicroscope tips useful for materials analysis in addition to being usedfor forming flexible interposers.

FIGS. 5A-5F illustrate a method for making a rigid interposer accordingto the present invention. The rigid interposer accommodates probing offlexible circuits that is often not accommodated by current interposertechnologies.

Referring to FIG. 5A, via holes 401 are formed in a wafer 400, forexample a silicon wafer. The via holes 401 may be etched as deep trenchvia holes within the wafer 400, for example, in a conventional manner asknown in the art. The vias holes 401 correspond to pad locations on adie to be tested and to pads located in packaging modules holding thedie.

Referring to FIG. 5B, the via holes 401 are filled with a conductivematerial to form conductive vias 402. The conductive material may be,for example, copper, copper paste, or solder, or other suitableconductive material known in the art.

Referring to FIG. 5C, a metal layer 403 is deposited on the wafer 400and the conductive vias 402 to form a wafer/metal layer combination 404.The metal layer 403 may be a thick copper layer.

Referring to FIG. 51), the wafer/metal layer combination 404 ispreferably thinned using conventional techniques to expose the bottom ofthe conductive vias 402, whereby front to back connections through thewafer 400 is provided by the conductive vias 402.

Referring to FIG. 5E, metal contacts 405 are then formed on the exposedvias 401 on the underside of the wafer. The metal contacts 405 may be inthe form or shape of bumps, for example, for contacting the pads on thepackaging module holding the chip. Of course, the artisan willappreciate that other shapes conducive to contacting the pads on thepackage holding the die may be used as the metal contacts 405 accordingto the invention.

Referring to FIG. 5F, probes 410 are then formed on upper side of thewafer/metal layer combination 404. Each of the probes 410 has aprojecting pin in the middle.

A schematic bird's eye view of one of the probes 410 is shown in moredetail in FIG. 6. An SEM image of one of the probes is shown in FIG. 7.The probes 410 contact the pads of the die under test. Each of theprobes 410 may comprises a pad 411 with a pin 412 in the middle of thepad 411. The pad 411 may be a recessed well such that the pin 412projects out from the well. The outer perimeter of the pad 411 thuscomprises a sharp, well-defined edge that in combination with therecessed well captures the solder pad of the die while the central pin412 punctures through oxides on the surface of the solder pad of thedie. Because the probes 410 are rigid and planar, when pressure isapplied to the rigid interposer against a flexible circuit duringprobing, the flexible circuit assumes the planarity of the rigidinterposer. As a result, a reliable connection between the pads of thedie being tested, the rigid interposer, and the packaging module isaccommodated.

To further enhance the ability of the probe pin 412 to puncture oxideson the surface of the solder pads of the die, the probe pin 412 may becoated with a hard material. The hard material may be tungsten ortitanium, for example, or other materials that can be electroplated,such as palladium-cobalt or palladium-nickel, for example.

Although the probes 410 may be comprised of other than silicon wafersaccording to the invention, the use of silicon wafers for the probes 410minimizes expense as silicon wafers are readily available and understoodin the semiconductor manufacturing industry. Likewise, the use ofsilicon wafers provides additional flexibility to the probes asadditional structures such as wiring structures or other active devices,for example, may be provided on either side of the probes. Suchadditional structures can provide for advanced probing techniquesincluding speed sorting.

Building the probes 410 on rigid substrates enable simplified alignmenttechniques relative to the solder pads of a die being tested or thepackaging modules holding said die. Additional and/or wider guide holescould be drilled along with the vias to enhance the mechanical alignmentof the probes 410 with the die and package modules. These holes wouldalign the probe pattern with nanometer accuracy to capture dowel pinsconnected to the substrate, for example, for very fast and accuratealignment of the probe with the die and packaging module.

While there has been shown and described what is considered to bepreferred embodiments of the invention, it will, of course be understoodthat various modifications and changes in form or detail could readilybe made without departing from the spirit and scope of the invention. Itis therefore intended that the invention be not limited to the exactforms described and illustrated herein, but should be construed to coverall modifications that may fall within the scope of the appended claims.

1. A flexible interposer comprising: a flexible interposer panelcomprising an insulator; at least one probe located on said flexibleinterposer panel and seeded with a first metal, wherein said at leastone probe comprises copper, and said first metal is Cu seeded with Pd; afirst electroless plated layer comprising a second metal that overliessaid first metal wherein said second metal is electrochemically morenoble than said first metal, and said second metal is Ni; and a secondelectroless plated layer comprising a third metal that overlies saidsecond metal, wherein said third metal is electrochemically more noblethan said second metal, said third metal is Au, and said firstelectroless plated layer and said second electroless plated layer arelocated on both sides of said flexible interposer panel.
 2. The flexibleinterposer of claim 1, further comprising electrically isolated regionslocated between said at least one probe, wherein said at least one probeis a plurality of probes.
 3. A flexible interposer comprising: asubstrate having a top surface and a bottom surface wherein first viascomprising a conductive material extend through said substrate betweensaid top surface and said bottom surfaces thereof, and a second set ofvia holes that are anisotropically etched along said bottom surface ofsaid substrate; a substrate insulating layer located on said bottomsurface of said substrate, said substrate insulating layer having thirdvia holes underneath a portion of said first vias; at least one flexiblelead having a tip in the shape of an inverted pyramid and a joining studabutting one of said first vias through one of said third via holes; andcontacts to said top surface of said substrate.
 4. The flexibleinterposer of claim 3, wherein said at least one flexible lead iscantilevered from said substrate.
 5. The flexible interposer of claim 4,further comprising wiring structures located on said contacts.
 6. Theflexible interposer of claim 5, wherein each of said at least oneflexible lead comprises an elastic metal coated with a conductive metal,wherein the combination of said elastic metal and said conductive metalhas high tensile properties.
 7. The flexible interposer of claim 5,wherein each of said at least one flexible lead comprises an elasticpolymer having a metal or metallic coating.
 8. The flexible interposerof claim 5, wherein each of said at least one flexible lead comprisesone of BeCu, W, Si and Si₃N₄.
 9. The flexible interposer of claim 5,wherein each of said at least one flexible lead comprises a rigidmaterial.
 10. The flexible interposer of claim 5, wherein said at leastone flexible lead is a plurality of flexible leads having a pitch fromabout 25 μm to about 400 μm.
 11. The flexible interposer of claim 10,wherein each of said at least one flexible lead has multiple tips in theshape of inverted pyramids.
 12. The flexible interposer of claim 11,wherein said multiple tips comprise an array for contacting a bump to beprobed.
 13. A flexible interposer comprising: a flexible interposerpanel comprising an insulator; at least one probe located on saidflexible interposer panel and seeded with a first metal; a firstelectroless plated layer comprising a second metal that overlies saidfirst metal; and a second electroless plated layer comprising a thirdmetal that overlies said second metal, wherein said first electrolessplated layer and said second electroless plated layer are located onboth sides of said flexible interposer panel.
 14. The flexibleinterposer of claim 13, wherein said at least one probe comprisescopper, said third metal is electrochemically more noble than saidsecond metal, and said second metal is electrochemically more noble thansaid first metal.
 15. The flexible interposer of claim 14, wherein saidfirst metal is Cu seeded with Pd, said second metal is Ni, and saidthird metal is Au.